Optimizing Interconnect for Performance in Standard Cell Library

Scaling in deep submicron era comes with additional baggage of increased interconnect impact on performance. With decreasing device sizes, interconnects start playing a dominant role in determining over all performance fall through that it is hard to ignore their role. Interconnects could take away performance as high as 50% from raw transistor. In this paper, we present a detailed study to establish performance sensitivities to each of the interconnect parasitic components on the standard cell libraries. The sensitivity results are then used to optimize cell layouts. Improvements on some of the library cells are demonstrated using this approach