Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits

A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with a pipelined multiplier verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance