A PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence

The design of PLD (programmable logic devices) used for various applications needs both high-speed and low-power operation. One of the design methods suited to this requirement is wave-pipeline technique. In this paper, we describe the wave-pipelining of PLD-design. This is applied to PRNG (pseudo-random number generator) circuit that is a sequential circuit. According to the result of the gate level simulation, the waved-PRNG circuit contributes to speed-up and low-power operation. In addition, this circuit is able to easily generate various random number sequences by controlling the operation clock frequency