A Novel Low-Power and High-Speed Master-Slave D Flip-Flop

A novel low-power and high-speed master-slave D flip-flop (MSDFF) is proposed in this paper. Without clocked inverter on critical path, the flip-flop operation speed has been improved. Employing the pseudo-NAND logic in the slave stage, the flip-flop has a smaller clock capacitance load, which helps to reduce the power consumption. The proposed flip-flop is verified with GSMC 1.5 V-0.15 mum CMOS technology. Compared with the widely used conventional D flip-flop, 48% power-delay-product (PDP) saving can be achieved, and both the power consumption and transition delay performance are better than many other flip-flops