A programmable parallel Huffman decoder

Huffman coding is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/sec presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. The paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 /spl mu/m CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-bit codeword lengths is estimated to run at 40 MHz with a chip area of 11 mm/sup 2/, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, the programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications.<>