Circuit Techniques for Gigabit/s Digital Communication Systems

This paper describes how mono1ithical1y integrated transistor pairs are used as hybrid circuit components to produce Gbit/s performance in digital communications equipment. The transistor technology results in a peak fT of 5GHz and includes gold beam-leads for easy circuit assembly. When used as current mode switches the pairs exhibit propagation delays and edge times of 350ps. The circuit technique is demonstrated in a number of key functions for regenerative repeaters and terminal/test equipment. These include clock extraction (phase detector), data regeneration (decision flip-flop), and multiplexing, all performing at IGbit/s. The multiplexer is used to seria1ise four lower speed data streams generated from a commercially available logic family and it is concluded that a new Gbit/s logic family may be unnecessary for this application.