A Clamping Circuit Architecture Implementing Charges Injection Reduction Techniques

By analyzing the classic clamping circuit, it is shown that the analog switches limit the precision of such a circuit, to 12 bits for 10Msamples/s signals, using a low-voltage CMOS 0.35mum technology. This paper presents an improved clamping architecture that overcomes these limitations. Precisions on the order of 16 bits and more can then be reached, the operational amplifiers being the new limiting factor