The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design

A new chip design paradigm, so called network on chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. In this paper, the H.264 decoder designed with three differently heterogenous tree-based network topologies are proposed. The topologies are designed so as to maximize the network throughput in accordance with the required transaction data between the functional modules of the H.264 decoder. This paper also evaluates these three topologies by comparing them to other regular topologies such as 2-D mesh and fat-tree with respects to throughput, power consumption and size. The simulated throughputs and various switch configurations are used as the inputs of the power modelling tool, known as Orion model. Hence, the static powers, areas, and dynamic energies of three topologies are calculated. The experiment results show that our tree-based topologies offer similar throughputs as fat-tree does and much higher throughputs compared to 2-D mesh while us less chip areas and power consumptions