10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC

Two-channel, 10-bit, 100-MS/s, time-interleaved pipelined ADC designed and fabricated in 0.18 mum CMOS technology is presented. Static gain mismatch between the channels is compensated for by background correlation scheme based on voltage injection without affecting the ADC input range. Dynamic gain mismatch due to incomplete linear settling in the front-end S/Hs is reduced by applying skew-insensitive sampling in the first stage of every pipelined ADC channel. Power consumption and chip area are minimized by using four-input opamps sharing and comparators' preamps sharing between each two consecutive stages. At sampling rate of 100 MS/s, this ADC achieves peak SNDR and SFDR of 57 dB and 69 dB respectively for a 3.99 MHz input signal, and consumes 75 mW from 1.8 V supply