A datapath compiler library for 0.7/spl mu/m CMOS

A rich library of custom datapath functions has been developed for a 0.7-/spl mu/m L/sub eff/ CMOS process, scalable to 0.55-/spl mu/m L/sub eff/. A well-balanced clock scheme, good power distribution mesh and optional ability to efficiently use a third layer of metal lend this library to high-performance applications. The library is well integrated into datapath compilation, datapath synthesis, chip estimation, and HDL generation tools.<>