A sub-50 psec. 89 K gate ECL-gate array with 480 Kb BiCMOS STRAM

A sub-50-ps low power ECL sea of cells gate array family with embedded high-speed/high-density BiCMOS self-timed RAM (STRAM) is described. The applied process technology has realized a maximum cut-off frequency of 23-GHz double polysilicon self-aligned bipolar transistor, 0.5-/spl mu/m triple-well CMOS transistor, and a maximum of five layers of Au metallization. An unloaded gate delay time of 36 ps with high-drive capability has been achieved using a novel active-pull-down emitter follower.<>