Multi Stream Cipher Architecture for Reconfigurable System-on-Chip

The post integration performance of cipher cores to a reconfigurable system-on-chip is a relatively unexplored area. There is also little work done on a stream aware cipher core. This paper presents an architecture that allows a cipher core to operate on multiple cipher streams without context switching. The integration of this architecture using fast simplex links to the microblaze soft-processor is examined in detail. Different communication protocols are examined and the numerical performance of the cipher in uClinux is discussed and analyzed.