A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access

In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an architecture optimized to handle flow processing tasks such as parsing, classification and packet manipulation. The VLIW instruction set allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment. Apart from scalability, programmability is also an important feature. Therefore, the processor is developed using a retargetable tool suite, creating the hardware and an optimized C compiler out of a single processor description