Behavioral Model based Simulation Methods for Charge-Pump PLL's

This paper discusses the ubiquitous problem of extremely long simulation times in transistor-level design of phase-locked loops (PLL). Methods for reducing time-domain simulation times arc presented. A Matlab simulation environment has been developed for the PLL simulations. Moreover, Spice macromodels for PLL building blocks have been introduced for achieving shorter time-domain Spice simulations. With these tools fast behavioural simulations, which are needed when dimensioning the PLL parameters, can be done in the Matlab environment, and the functionality of transistor level design of PLL blocks can be verified by a time-domain analysis in a reasonably short time