A Random Projection Imager for Visual Pattern Classification in Analog VLSI

In this paper, we present a novel CMOS imager architecture that implements the random projection dimensionality reduction algorithm in the focal plane. We employ analog signal processing techniques to achieve low-power operation and our imager can readily integrate with known low-power VLSI classifiers. We fabricated a 20 times 20 pixel prototype of our 4.2mm² imager in 0.35 mum CMOS that performs 1GOPS while consuming 1.25mW of power from a 5V supply