Low Power Sampling Latch for up to 25 Gb/s 2x Oversampling CDR in 90-nm CMOS

A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10^-12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a snail area of 30times20 mum²