Multi-bit MIN unit for direct data stream architecture fuzzy logic controllers

This paper presents the design and development of multi-bit minimum (MIN) unit. Such a unit is necessary to efficiently implement the direct data stream (DDS) architecture of fuzzy logic controllers. The mathematical background as well as circuit design, verification, and simulation is described. The advantage of this design is its scalability, as the number of input bits per vector can be increased with a step of four-at a minimal increase in computational rates. These simulation results (standard cells implemented with 2 /spl mu/m CMOS technology) were confirmed with Mentor Graphics' professional IC design tools.<>