Low Power High Speed Domino Logic based on Double Capacitive Body Biased Keeper

In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor adapts to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper (SCBBK). All the various body bias circuits are applied to a wide fan in OR domino gate for evaluating delay time, power consumption, power-delay product (PDP) and noise immunity. The simulation results for 0.18 mum Hynix CMOS technology show that DCBBK reduces 44%, 20%, 9% in power compare to SD, DBBK, SCBBK while DBBK, SCBBK, DCBBK improve 46% in speed than SD gate