Design and modelling of a low phase noise pll frequency synthesizer

This paper focuses on the low VCO sensitivity gain design, and modeling of a low phase noise 2.4GHz PLL frequency synthesizer. Tuning switch array is used in the LC tank to achieve low VCO gain and wide tuning rang simultaneously. The digital switch effects to phase noise have been analyzed in this paper. Moreover, a new method is provided for modeling and predicting phase noise of the frequency synthesizer. It overcomes the overall PLL noise analysis problem caused by large divider ratios. Simulation results show the synthesizer overall phase noise is -123.6dBc/Hz at 1MHz frequency offset. The PLL frequency synthesizer has been implemented in a standard 0.18mum CMOS technology