Design of Dual-mode Equalizer for QAM Demodulator in FPGA

This paper deals with the design of a dual-mode equalizer for QAM demodulator in FPGA. The fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock rate. The equalizer can also be configured to handle spectrum inversion. Meanwhile we optimize the implementation architecture to reduce hardware complexity. Test results show that the equalizer can achieve high reliability at low hardware costs