Logic Analysis of High-speed MOBILE Circuit

The logic of monostable-bistable transition logic element (MOBILE) is analyzed based on the equivalent circuit model. The peak current ratio of RTDs affects the switching time of the circuit. Improper selection of V_dd will lead to incorrect logic function or longer switching time. The failure in a short rising time condition is explained by the comparison of the output voltage at t = tr with the potential peak voltage. It dominates the circuit behavior under high-speed operation. We also calculate the maximum allowed load capacitance, below which the switching time is linear proportional with the value of load capacitance