Generation-Recombination-Trapping at Interface Traps In Compact MOS Transistor Modeling

Operation lifetime of logic MOS transistors, endurance of memory MOS transistors, trapping noise in analog and RF MOS transistors, and standby power dissipation in all of these transistors, have their common origin in electron-hole GRT (generation-recombination-trapping) at SiO ₂/Si interface traps. Inclusion of GRT in MOS transistor model can be made using the surface-potential approach adopted by the next (second) generation compact model. This paper describes the theoretical analysis of the GRT currents in the long-wide-channel MOS transistor model to serve as the baseline for compact modeling