Novel SJ-LDMOS with partial N-buried layer for SPIC applications

A novel super-junction (SJ) LDMOS (SJ-LDMOS) with partial N-buried layer is proposed which allows high breakdown voltage (BV) and low on-resistance (Ron). The proposed structure overcomes the substrate-assisted-depletion effect thus achieving the charge compensation between the n and p pillars as well as a uniform electric field distribution in the drift region in the off-state. The N-buried layer also provides a low current path in the on-state. In addition, the proposed device is compatible with smart power technology