Mobility enhancement technology

The appropriate external stress can enhance device and circuit performance. The 7.4% speed enhancement is achieved for the 250 nm node ring oscillator under uniaxial tensile strain for mutually perpendicular layout of the NFET and the PFET. The speed enhancement is less than 1.5% for the conventional parallel layout of the NFET and the PFET. The ultra thin strained Si_0.2Ge_0.8 quantum well channel (~5 nm) directly grown on Si substrate is also demonstrated. The SiGe quantum well channel using Pt Schottky barrier and SiO₂ gate dielectrics reveals a ~3.2times current enhancement and ~3times mobility enhancement as compared to the bulk Si PFET. The compressive strain on SiGe quantum well can further enhance the hole mobility in Si _0.2Ge_0.8 channel