Low power CMOS clock buffer

Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its area requirement below those that are achievable by the traditional tapered CMOS buffers.<>