A single chip implementation of receive path termination for SONET OC-12c and quadruple SONET OC-3c

Receive Path Termination in a SONET network is required to perform the path level functionality. The Synchronous Payload Envelope (SPE) of a SONET frame must first be located using the payload pointers in the SONET Line overhead. Once the SPE is located, the path termination device must keep track of it and provide information to higher level protocols about its location and status. While the most crucial functionality must be handled in hardware, the entire overhead information is stored for processing by a line card processor. The incoming SONET stream is processed in words of 32 bits each. The quadruple OC-3c mode (OC-12) occupies almost an entire Xilinx XC 3195 Field Programmable Gate Array (FPGA). The SONET OC-12c mode processing takes fewer gates but requires the large chip to perform a Bit Interleaved Parity (BIP) check on the SPE. The interface to both designs is physically identical and they can form a part of a line card that is capable of two distinct modes of operation.<>