A formal approach to pipeline optimization in synthesis of digital signal processors with fine grain parallelism

In this paper we present a constraint-model for pipelined digital signal processors, based on mathematical programming. Our intention is to maximize the utilization of allocated hardware components by minimizing the clock-cycle time and the period of cyclic innermost loop schedules in one approach. The constraint formulations are developed for a very general multiphase clocking environment with an FPGA (Field Programmable Gate Array) target architecture.<>