Capacitive Gate Insulator Thickness and Its Impact on Static and Dynamic Behavior of Scaled PD-SOI-MOSFET

The influence of technological parameters on the capacitive gate insulator thickness and the electrical transistor behavior of different technology nodes were simulated. Starting from calibrated PD-SOI-transistors, designed for the 130 nm technology, scaled 45 nm technology transistors were examined. The inverter propagation delay time and corresponding saturation drive currents of different technologies with varying gate insulator thicknesses were compared under the aspect of manufacturability. Further improvements due to the implementation of metal gates were estimated