A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design

A V_th variation has large impact on SRAM operation. To predict an SRAM operating margin in design phase, a V_th window analysis is used. We propose an improved V_th window analysis, which considers a relationship between global and local V_th variation, and the analysis enables accurate operating margin prediction. This analysis predicts 7.7% larger yield deterioration than conventional method in 65-nm manufacturing process and gives a chance to introduce some operating margin enhancement circuits in design phase.