Strain Effects on Quasi-Bound State Tunneling in Advanced SOI CMOS Technologies

We study the influence of uniaxial <110> stress on the gate leakage current in advanced silicon-on-insulator (SOI) CMOS devices. The strain-induced shifts of the conduction band valleys and the valence bands are calculated using linear deformation potential theory. After the evaluation of the band edge profile, using a numerical Schrodinger Poisson (S/P) solver, the leakage current is estimated with the quasi-bound states tunneling formalism in a post processing step. The energy shifts of the primed and unprimed subband ladders due to the applied stress yield a re-population of the subbands. This results in a slight decrease for tensile stress and an increase for compressive stress of the leakage current, respectively. These results are in agreement with experimental studies on n-MOS devices