Advanced Packages and Board Level Reliability

Many research projects have been taken in the international arena to study the preconditions for a successful implementation in the lead-free interconnection technology. The paper dedicated specially to this topic, which is of relevant importance to the electronics industry. The coverage is focused primarily to the I/O level, size and constitution of advanced packages, their material related influence on the process ability and the reliability later on on the product level. For that reason data will be presented and discussed describing the thermal (in-) stability and their interaction to the laminates used for the assembly process. Furthermore the ball- and/or pre-plated bump-materials will be discussed influencing the board level reliability. While a significant amount of research and qualification work has been conducted in recent years on manufacturing and reliability issues to enable the conversion to lead-free technologies, data from studies related to the reliability of lead-free interconnects at advanced packages are still emerging. Furthermore temperature profiling (based on DSC and RASH) and interconnection quality based on lead-free finishes and interaction with lead-free solders, the wetting behavior compared to board and component finishes and surface tension will be presented. A comparison between SAC and SP, process analysis of advanced packages (thermal analysis and deflection under reflow conditions), assembly results (topology, X.ray, microsections), inspection criterias, testboards/demonstrators/acceptance criteria (SnPb vs. SnAgCu) is integrated as well. Components with lead-free finishes/interconnection quality, Area Array (EGA, CSP, FC) with lead-free balls, the resulting interconnection quality and reliability (TCT, HHT, NTS), results after non-destructive and destructive evaluation and damage mechanisms (crack initiation and growth) will be discussed