Temporal Placement for Run-Time Reconfiguration

In this paper, we propose the use of an algorithm that can improve the performance of the FPGA placement task for run-time reconfiguration (RTR) computing. Previous literature can be referenced for the sake of presenting related work, as well as to present some algorithms that can be used for the placement of static, compile-time reconfigurable devices. These algorithms can then be examined in order to propose a placement algorithm that can be used in further RTR research