A 200-MHz CMOS bit-serial neural network

Implementing neural network hardware is a challenging task with tough requirements on computation and communication. We explore a time-multiplexed architecture with both bit-serial communication and computation, SINN (Serially Implemented Neural Network), for which the main goal is a high computation/area ratio. On-chip learning is excluded since this is a waste of hardware resources during run-time for many applications. Our experience is that an optimized bit-serial implementation has smaller area, while power consumption is increased, compared to a parallel structure.<>