Regular processor arrays with data-dependent dependencies

The authors present a model for data-dependent data-flow in regular processor arrays. This model is suitable for parallel implementation of nested-loop programs in which all but a few of the dependencies are constant. The model consists of a regular data routing architecture that matches the regular architecture of the deterministic part of the nested-loop program so that they can be merged. Due to the data-dependent behavior of the router part of the architecture, this part has to operate asynchronously.<>