Channel-Calculating Logic for a TV Tuning System

A digital television receiver tuning circuit has been developed. The circuit accepts multiplexed BCD channel numbers from any user control circuit providing data in that format. When a new channel is called for, the acquisition time is minimized by rapidly sweeping a voltage-controlled local oscillator until over-shoot of the desired frequency is detected and then switching to phase-locked-loop operation to achieve exact tuning. In the PLL mode, the local oscillator frequency is divided by a modulus that depends on the channel number. The logic provides a variable modulus by presetting a counter to a state common to all channels in the band and counting until a match to the desired channel number is obtained. Operation in the channel number domain substantially reduces the amount of ROM required in contrast to other techniques. The counter output is compared to a reference frequency and frequency/phase comparator output pulses produce changes in the tuning voltage to keep the local oscillator tuned to the standard channel frequency. Although PLL operation is adequate in most environments, nonstandard carrier frequencies must be accommodated. A local option switch permits release to a conventional AFC after the PLL has tuned exactly to the standard channel frequency. In the AFC mode, the digital system monitors the local oscillator and initiates a tuning cycle only if the frequency deviates from the standard frequency by a prescribed amount. Careful attention to speed considerations and partitioning have permitted this circuit to be achieved in a custom PMOS IC with only 18 pins.