Implementation of High Data Rate Stream Parsing with Data Aligning Mechanism

Nowadays the HDTV (high definition television) is growing more and more popular. In many cases a compression of this high quality multimedia data is needed for storing or transmitting purposes. In order to preserve good quality, the compressed stream should have high data rate. It is also common case to combine several such streams, representing different programs, into one single multimedia stream. Here comes the need of high data rate multiplexing and demultiplexing. To operate with high data rate stream, the clock frequency, the word width or both have to be increased. For cost efficient FPGA implementation the wider word width is preferred, which allows smaller in logic and slower in speed FPGA to be used. In this paper the issues following this choice are revealed and a data aligning implementation technique is proposed