A Runtime Reconfigurable Architecture for Viterbi Decoding

This paper presents the design and implementation of a runtime reconfigurable architecture for Viterbi decoding with a high throughput rate suitable for software defined radio (SDR). SDR is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. The architecture can be reconfigured to decode convolutionally coded data with constraint lengths from 3 to 7 and code rates 1/2 and 1/3. Reconfiguration of the architecture does not require FPGA reprogramming. With a throughput of 70 Mbps, the proposed decoder is suitable for use in receiver architectures of 802.11a, 802.16, 3G and GSM