Elimination of Single Event Latchup in 90nm SRAM Technologies

We present a comprehensive review of design as well as process options to completely eliminate soft error induced single event latchup (SEL) in modern CMOS based SRAM technologies under datasheet operating conditions. The detailed mechanism of latchup under radiation environment is discussed and analyzed. EPI substrate starting material and the use of a triple well architecture are selected as process technology options to eliminate SEL. In addition to the process options we present a superior circuit option to quench out single event latchup. The options have been implemented on 90nm and validated on multiple experimental nuclear testing sites