Digital Encoders for High Speed Flash-ADCs: Modeling and Comparison

Digital encoders are a known bottleneck for high speed flash-ADC architectures. This paper describes a survey of various thermometer-to-binary code (TC-to-BC) decoders. Wallace tree decoder is found to be the best among others in terms of bubble error correction but it consumes more power for multigiga hertz applications. Authors present that TC-to-BC decoder based on feedforward neural network structure cascaded with bit-swapping technique can achieve almost same level of performance for bubble error correction and consumes less power. The proposed implementation is suitable for CMOS process technology which is considered very economic solution in integrated circuits (IC) process industry