A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems

A pulse-triggered D flip-flop with an embedded clock-gating scheme that is suitable for low-power high-speed synchronous applications is presented in this paper. Various flip-flops and different proposed clock-gating circuits were simulated to determine and compare their performance in terms of speed and power dissipation, in order to obtain the best featured one. The circuits were designed using a 0.35 mum CMOS technology and supplied with 3.3 V. As shown in HSPICE simulations, the proposed flip-flop operates up to 1.25 GHz with a delay of 0.3 ns and a power dissipation of 4.1 mW, and it leads to power savings around 45% when used to build a 16-bits binary counter, compared to the counter that uses the non-gated version of the pulse-triggered flip-flop