Challenges for process and product integration at 45nm

Abstract form only given. To fully realize the benefits of CMOS scaling, new process generations must reach high yield at low cost, rapidly. Product design faces both higher complexity of process integration, including geometrical effects like strain engineering, as well as a larger need to accurately predict many systematic and random variations. These design-for-manufacturing challenges force an unprecedented interaction of physical design and process optimization for the first generation of 45nm CMOS systems