An experimental investigation on the performance of plastic packages for power integrated circuits in presence of high electric stresses

This paper describes an investigation about the possibilities offered by plastic packages for integrated circuits to be used in "high voltage" applications, i.e. at a service voltage much higher than usual. The experiment has been focused on test patterns manufactured modifying the lay-out of commercial packages without changing the manufacturing technology and the epoxy encapsulant. Long term and short term test results indicate that an adequate choice of the interelectrode distances is sufficient to avoid electrical degradation during the normal service life of the real components.<>