PLANE: A new ATPG system for PLAs

In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.<>