Study and characterization of photosensitive cells in ASICs

This paper describes a full custom ASIC realization of different kinds of photosensitive cells in a CMOS 1.2 /spl mu/m and two levels of metal technology which is normally used for the design of digital data processing architectures (ES2). Each cell is directly controlled by a MOS transistor and the photocurrent produced by a luminous flux can be modulated by applying an appropriate gate voltage. The objective of the study and characterization of such cells is to design a array of photosensitive cells where a current directly proportional to the incident luminous flux is produced for each cell. Besides the integration time, or exposure time, and the instant the electrical information is read are different for each cell (or pixel) and independent of its location in the array. The authors first present the results obtained by a static study (e.g. under a constant luminous flux) before discussing the dynamic analysis where the discharge of the photodiode capacitor has been studied as a function of the luminous flux, the integration time and the reading moment. Moreover, the active surface area as well as the design techniques are also been considered in the authors' comparison criteria.<>