A low-complexity bit-serial DCT/IDCT architecture

A novel DCT/IDCT (discrete cosine transform/inverse DCT) dataflow architecture is presented allowing the efficient implementation of one hardware unit, which has only positive-valued multiplier coefficients and can be switched to perform either the DCT or the IDCT. The MSB (most significant bit)-first carry-save arithmetic introduced allows the design of extremely efficient solutions with low processing delay and high precision, which support medium-to-low-speed transform rates. The results of the H.261 precision compliant CMOS realization prove the hardware efficiency of this architecture.<>