HBT gate array for 5 GHz ASICs

A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<>