Reducing the physical design cycle by means of topological placement with hard timing restraints

A new concept for topological module placement satisfying hard timing restraints based on segmenting the layout surface into topological rings is introduced. By using this method it is possible to shorten the layout-extraction-relayout cycle significantly, because the resulting placement satisfies user defined signal run-times. The new method can be applied to hierarchical layout systems, and is flexible in terms of design styles and module specifications.<>