A single chip high data rate QPSK demodulator

A single chip VLSI design of a digital quadrature-phase-shift-keying (QPSK) demodulator for satellite communication purposes is presented. The digital demodulator uses an optimized phase recovery scheme suitable for single chip implementation. It also uses an efficient timing recovery scheme based on XOR transition detection. The demodulator is suitable for time-division-multiplexing (TDM) applications and can give a speed of 50 Mbps.<>