Time efficient method for MOS circuit extraction

A new method for circuit extraction from VLSI masks for any MOS technology is presented. The algorithms operate on mask edges allowing rapid connectivity and device extraction. A new approach to non rectilinear polygon overlap analysis is presented. The scanline algorithm used is modified to meet geometric features imposed by technology. The transistor extraction is based on analysis of oriented, polygonal forms, allowing simultaneous transistor recognition and extraction of its topological parameters. The algorithms enable faster circuit extraction than previously presented methods, and, at the same time, are easy to understand and to implement.<>