Modified probabilistic RAM architecture for VLSI implementation of a backpropagation learning algorithm

A network based on the modified probabilistic RAM architecture is proposed for VLSI implementation with on-chip learning capability. The pRAM structure is modified for the computation of error backpropagation and weight updates, where the multiplication and summations are performed with simple AND gates and OR gates, respectively. The simulation results for the derived algorithm are discussed, and a VLSI implementation of the pRAM for backpropagation is also explained.<>